《二位元多工器》

module top;

wire A0, A1, B0, B1, SEL , NOT_SEL , X , Y , Z, W, OUT0, OUT1;

system_clock #1600 clock1(A0);
system_clock #800  clock2(A1);
system_clock #400  clock3(B0);
system_clock #200  clock4(B1);
system_clock #100  clock5(SEL);

not n1(NOT_SEL, SEL);
and a1(X, A0, SEL);
and a2(Y, A1, SEL);
and a3(Z, B0, NOT_SEL);
and a4(W, B1, NOT_SEL);
or o1(OUT0, X , Z);
or o2(OUT1, Y , W);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>2000)$stop;
endmodule

《1位元多工器》(Not接角對掉)

module top;


wire A, B, Sel, Not_Sel, X, Y, OUT;

system_clock #400 clock1(A);
system_clock #200 clock1(B);
system_clock #100 clock1(Sel);

not n1(Not_Sel,Sel);

and a1(X, A, Not_Sel);
and a2(Y, B, Sel);

or o1(OUT, X, Y);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

《1位元多工器》

module top;


wire A, B, Sel, Not_Sel, X, Y, OUT;

system_clock #400 clock1(A);
system_clock #200 clock1(B);
system_clock #100 clock1(Sel);

not n1(Not_Sel,Sel);

and a1(X, A, Sel);
and a2(Y, B, Not_Sel);

or o1(OUT, X, Y);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

《2AND》

module top; 

wire A, B, OUT, C, F;

system_clock #400 clock1(A); 

system_clock #200 clock2(B);

system_clock #100 clock3(C);

and a1(OUT, A, B);

and a2(F,OUT,C);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk; 

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

《AND邏輯閘測試》

module top;


wire A, B, OUT;
system_clock #400 clock1(A);
system_clock #200 clock2(B);

and a1(OUT, A, B);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule