《1位元多工器》

module top;


wire A, B, Sel, Not_Sel, X, Y, OUT;

system_clock #400 clock1(A);
system_clock #200 clock1(B);
system_clock #100 clock1(Sel);

not n1(Not_Sel,Sel);

and a1(X, A, Sel);
and a2(Y, B, Not_Sel);

or o1(OUT, X, Y);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule