《二位元多工器》

module top;

wire A0, A1, B0, B1, SEL , NOT_SEL , X , Y , Z, W, OUT0, OUT1;

system_clock #1600 clock1(A0);
system_clock #800  clock2(A1);
system_clock #400  clock3(B0);
system_clock #200  clock4(B1);
system_clock #100  clock5(SEL);

not n1(NOT_SEL, SEL);
and a1(X, A0, SEL);
and a2(Y, A1, SEL);
and a3(Z, B0, NOT_SEL);
and a4(W, B1, NOT_SEL);
or o1(OUT0, X , Z);
or o2(OUT1, Y , W);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>2000)$stop;
endmodule